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a ad5301/ad5311/ad5321 * information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. rev. a 2.5 v to 5.5 v, 120 a, 2-wire interface, voltage output 8-/10-/12-bit dacs functional block diagram resistor network buffer v out dac register power-down logic ad5301/ad5311/ad5321 v dd scl a0 gnd a1 * ref power-on reset pd * sda * available on 8-lead version only 8-/10-/12-bit dac interface logic features ad5301: buffered voltage output 8-bit dac ad5311: buffered voltage output 10-bit dac ad5321: buffered voltage output 12-bit dac 6-lead sot-23 and 8-lead msop packages micropower operation: 120 a @ 3 v 2-wire (i 2 c compatible) serial interface data readback capability 2.5 v to 5.5 v power supply guaranteed monotonic by design over all codes power-down to 50 na @ 3 v reference derived from power supply power-on reset to 0 v on-chip rail-to-rail output buffer amplifier 3 power-down functions applications portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators general description the ad5301/ad5311/ad5321 are single 8-bit, 10-bit, and 12-bit buffered voltage-output dacs that operate from a single 2.5 v to 5.5 v supply, consuming 120 a at 3 v. the on-chip output am plifier allows rail-to-rail output swing with a slew rate of 0.7 v/ s. it uses a 2-wire (i 2 c compatible) serial interface that operates at clock rates up to 400 khz. multiple devices can share the same bus. the reference for the dac is derived from the power supply inputs and thus gives the widest dynamic output range. these parts incorporate a power-on reset circuit, which ensures that the dac output powers-up to 0 v and remains there until a valid write takes place. the parts contain a powe r-down feature that reduces the current consumption of the device to 50 na at 3 v and provides software-selectable output loads while in power-down mode. the low power consumption in normal operation make these dacs ideally suited to portable battery-operated equipment. the power consumption is 0.75 mw at 5 v and 0.36 mw at 3 v, reducing to 1 w in all power-down modes. * protected by u.s. patent no. 5684481, other patent pending.
rev. a e2e ad5301/ad5311/ad5321especifications v dd = 2.5 v to 5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted. b version 2 parameter 1 min typ max unit conditions/comments dc performance 3, 4 ad5301 resolution 8 bits relative accuracy 0.15 1 lsb differential nonlinearity 0.02 0.25 lsb guaranteed monotonic by design over all codes. ad5311 resolution 10 bits relative accuracy 0.5 4 lsb differential nonlinearity 0.05 0.5 lsb guaranteed monotonic by design over all codes. ad5321 resolution 12 bits relative accuracy 2 16 lsb differential nonlinearity 0.3 0.8 lsb guaranteed monotonic by design over all codes. zero-code error 5 20 mv all zeros loaded to dac, see figure 9. full-scale error 0.15 1.25 % of fsr all ones loaded to dac, see figure 9. gain error 0.15 1% of fsr zero-code error drift 5 e20 v/ c gain error drift 5 e5 ppm of fsr/ c output characteristics 5 minimum output voltage 0.001 v min this is a measure of the minimum and maximum drive maximum output voltage v dd e 0.001 v max capability of the output amplifier. dc output impedance 1 short-circuit current 50 ma v dd = 5 v. 20 ma v dd = 3 v. power-up time 2.5 s coming out of power-down mode. v dd = 5 v. 6 s coming out of power-down mode. v dd = 3 v. logic inputs (a0, a1, pd dd dd dd dd dd dd p pd dd dd dd dd dd pw pd pw dd dd d dd d dd dd d dd dd d dd pd dd dd d dd dd d d ddd d
rev. a 3 ad5301/ad5311/ad5321 ac characteristics 1 b version 3 parameter 2 min typ max unit conditions/comments output voltage settling time v dd = 5 v ad5301 6 8 s 1/4 scale to 3/4 scale change (40 hex to c0 hex) ad5311 7 9 s 1/4 scale to 3/4 scale change (100 hex to 300 hex) ad5321 8 10 s 1/4 scale to 3/4 scale change (400 hex to c00 hex) slew rate 0.7 v/ s major-code change glitch impulse 12 nv-s 1 lsb change around major carry digital feedthrough 0.3 nv-s notes 1 see terminology section. 2 guaranteed by design and characterization, not production tested. 3 temperature range is as follows: b version: ?0 c to +105 c. specifications subject to change without notice. timing characteristics 1 limit at t min , t max parameter 2 (b version) unit conditions/comments f scl 400 khz max scl clock frequency t 1 2.5 s min scl cycle time t 2 0.6 s min t high , scl high time t 3 1.3 s min t low , scl low time t 4 0.6 s min t hd,sta , start/repeated start condition hold time t 5 100 ns min t su,dat , data setup time t 6 3 0.9 s max t hd,dat , data hold time 0 s min t 7 0.6 s min t su,sta , setup time for repeated start t 8 0.6 s min t su,sto , stop condition setup time t 9 1.3 s min t buf , bus free time between a stop condition and a start condition t 10 300 ns max t r , rise time of both scl and sda when receiving 0 ns min may be cmos driven t 11 250 ns max t f , fall time of sda when receiving 300 ns max t f , fall time of both scl and sda when transmitting 20 + 0.1c b 4 ns min c b 400 pf max capacitive load for each bus line notes 1 see figure 1. 2 guaranteed by design and characterization, not production tested. 3 a master device must provide a hold time of at least 300 ns for the sda signal (referred to the v ih min of the scl signal) in order to bridge the undefined region of scl? falling edge. 4 c b is the total capacitance of one bus line in pf. t r and t f measured between 0.3 v dd and 0.7 v dd . specifications subject to change without notice. v dd = 2.5 v to 5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted. v dd = 2.5 v to 5.5 v. all specifications t min to t max , unless otherwise noted.
rev. a ad5301/ad5311/ad5321 ? ordering guide temperature package package model range description option branding ad5301brm-reel ?0 c to +105 c msop rm-8 d8b ad5301brm-reel7 ?0 c to +105 c msop rm-8 d8b ad5301brt-500rl7 ?0 c to +105 c sot-23 rt-6 d8b ad5301brt-reel ?0 c to +105 c sot-23 rt-6 d8b ad5301brt-reel7 ?0 c to +105 c sot-23 rt-6 d8b ad5301brtz-500rl7 * ?0 c to +105 c sot-23 rt-6 d8b ad5301brtz-reel * ?0 c to +105 c sot-23 rt-6 d8b ad5301brtz-reel7 * ?0 c to +105 c sot-23 rt-6 d8b ad5311brm-reel ?0 c to +105 c msop rm-8 d9b ad5311brm-reel7 ?0 c to +105 c msop rm-8 d9b ad5311brt-500rl7 ?0 c to +105 c sot-23 rt-6 d9b ad5311brt-reel ?0 c to +105 c sot-23 rt-6 d9b ad5311brt-reel7 ?0 c to +105 c sot-23 rt-6 d9b ad5321brm-reel ?0 c to +105 c msop rm-8 dab ad5321brm-reel7 ?0 c to +105 c msop rm-8 dab ad5321brt-500rl7 ?0 c to +105 c sot-23 rt-6 dab ad5321brt-reel ?0 c to +105 c sot-23 rt-6 dab ad5321brt-reel7 ?0 c to +105 c sot-23 rt-6 dab absolute maximum ratings 1, 2 (t a = 25 c, unless otherwise noted.) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v scl, sda to gnd . . . . . . . . . . . . . . . . ?.3 v to v dd + 0.3 v pd , a1, a0 to gnd . . . . . . . . . . . . . . . ?.3 v to v dd + 0.3 v v out to gnd . . . . . . . . . . . . . . . . . . . . ?.3 v to v dd + 0.3 v operating temperature range industrial (b version) . . . . . . . . . . . . . . . . 40 c to +105 c storage temperature range . . . . . . . . . . . . . ?5 c to +150 c junction temperature (t j m ax) . . . . . . . . . . . . . . . . . . . . 150 c sot-23 package power dissipation . . . . . . . . . . . . . . . . . . . (t j m ax ?t a )/ ja ja thermal impedance . . . . . . . . . . . . . . . . . . . . 229.6 c/w sop package power dissipation . . . . . . . . . . . . . . . . . . . (t j m ax ?t a )/ ja ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 206 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch-up. t 9 t 4 t 6 t 5 t 7 t 8 t 1 t 2 t 4 t 11 t 10 t 3 start condition repeated start condition stop condition sda scl figure 1. 2-wire serial interface timing diagram * z = pb-free part. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. al though the ad5301/ad5311/ad5321 features proprietary esd protection circuitry, perma nent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. a ad5301/ad5311/ad5321 ? pin configurations 6-lead sot-23 (rt-6) top view (not to scale) 6 5 4 1 2 3 gnd sda scl v dd a0 v out ad5301/ ad5311/ ad5321 8-lead msop (rm-8) top view (not to scale) 8 7 6 5 1 2 3 4 a0 pd v out gnd v dd scl sda a1 ad5301/ ad5311/ ad5321 pin function description msop sot-23 pin no. pin no. mnemonic function 16v dd power supply input. these parts can be operated from 2.5 v to 5.5 v and the supply should be decoupled with a 10 f in parallel with a 0.1 f capacitor to gnd. 25 a0 address input. sets the least significant bit of the 7-bit slave address. 3 n/a a1 address input. sets the second least significant bit of the 7-bit slave address. 44v out buffered analog output voltage from the dac. the output amplifier has rail-to-rail operation. 5 n/a pd active low control input that acts as a hardware power-down option. this pin overrides any software power-down option. the dac output goes three-state and the current consumption of the part drops to 50 na @ 3 v (200 na @ 5 v). 63 scl serial clock line. this is used in conjunction with the sda line to clock data into the 16-bit input shift register. clock rates of up to 400 kbit/s can be accommodated in the i 2 c compat- ible interface. scl may be cmos/ttl driven. 72 sda serial data line. this is used in conjunction with the scl line to clock data into the 16-bit input shift register during the write cycle and to read back one or two bytes of data (one byte for the ad5301, two bytes for the ad5311/ad5321) during the read cycle. it is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor. if not used in readback m ode, sda may be cmos/ttl driven. 81 gnd ground reference point for all circuitry on the part.
rev. a ad5301/ad5311/ad5321 e6e terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the actual endpoints of the dac transfer function. typical inl vs. code plots can be seen in figures 2 to 4. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb m aximum ensures monotonicity. these dacs are guaranteed monotonic by design over all codes. typical dnl vs. code plots can be seen in figures 5 to 7. zero-code error zero-code error is a measure of the output error when zero code (00h) is loaded to the dac register. ideally, the output should be 0 v. the zero-code error of the ad5301/ad5311/ad5321 is always positive because the output of the dac cannot go below 0 v. it is due to a combination of the offset errors in the dac and output amplifier. it is expressed in mv, see figure 9. full-scale error full-scale error is a measure of the output error when full scale is loaded to the dac register. ideally, the output should be v dd e 1 lsb. full-scale error is expressed in percent of fsr (full-scale range). a plot can be seen in figure 9. gain error this is a measure of the span error of the dac. it is the devia- tion in slope of the actual dac transfer characteristic from the ideal expressed as a percentage of the full-scale range. zero-code error drift th is is a measure of the change in zero-code error with a change in tem perature. it is expressed in v/ c. gain error drift this is a measure of the change in gain error with changes in tem- perature. it is expressed in (ppm of full-scale range)/ c. major code transition glitch energy major code transition glitch energy is the energy of the impulse injected into the analog output when the code in the dac regis- ter changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital code is changed by 1 lsb at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital input pins of the device but is measured when the dac is not being written to. it is specified in nv-s and is measured with a full-scale change on the digital input pins, i.e., from all 0s to all 1s and vice versa.
rev. a ad5301/ad5311/ad5321 e7e t ypical performance characteristicse code inl error (lsb) 1.0 0.5 e1.0 050 250 100 150 200 0 e0.5 t a = 25 c v dd = 5v figure 2. ad5301 typical inl plot code dnl error (lsb) 0.3 e0.3 050 250 100 150 200 e0.1 e0.2 0.2 0.1 0 t a = 25 c v dd = 5v figure 5. ad5301 typical dnl plot temperature ( c) error (lsb) 1.00 0.75 e1.00 e40 0 120 40 80 0 e0.25 e0.50 e0.75 0.50 0.25 v dd = 5v max inl max dnl min dnl min inl figure 8. ad5301 inl error and dnl error vs. temperature code inl error (lsb) 3 0 200 1000 400 600 800 0 e1 e2 e3 2 1 t a = 25 c v dd = 5v figure 3. ad5311 typical inl plot code dnl error (lsb) 0.3 e0.3 0 200 1000 400 600 800 e0.1 e0.2 0.2 0.1 0 t a = 25 c v dd = 5v figure 6. ad5311 typical dnl plot temperature ( c) e40 0 100 40 80 10 8 6 4 2 0 e2 e4 e6 e8 e10 60 20 e20 zero scale full scale v dd = 5v error (mv) figure 9. zero-code error and full- scale error vs. temperature code inl error (lsb) 12 0 1000 4000 2000 3000 0 e4 e8 e12 8 4 t a = 25 c v dd = 5v figure 4. ad5321 typical inl plot t a = 25 c v dd = 5v code dnl error (lsb) 1.0 0.5 e1.0 0 1000 4000 2000 3000 0 e0.5 figure 7. ad5321 typical dnl plot i dd ( a) frequency (hz) 120 200 v dd = 5v v dd = 3v 180 160 140 100 80 figure 10. i dd histogram with v dd = 3 v and v dd = 5 v
rev. a ad5301/ad5311/ad5321 e8e i (ma) v out (v) 5 0 03 6 3 2 1 4 15 5v source 3v source 3v sink 5v sink 912 figure 11. source and sink current capability v dd (v) 1.0 0 2.7 3.2 5.2 3.7 4.2 4.7 0.4 0.2 0.8 0.6 i dd ( a) e40 c +25 c +105 c figure 14. power-down current vs. supply voltage ch1 1v, ch2 1v, time base = 20 s/div ch2 ch1 v dd v out t a = 25 c figure 17. power-on reset to 0 v i dd ( a) 200 zero scale full scale 180 160 140 120 100 80 60 40 20 0 code v dd = 5v v dd = 3v t a = 25 c figure 12. supply current vs. code v logic (v) 300 0 0 150 100 250 200 i dd ( a) 1.0 2.0 3.0 4.0 5.0 50 t a = 25 c v dd = 5v v dd = 3v increasing decreasing figure 15. supply current vs. logic input voltage for sda and scl volt- age increasing and decreasing ch1 1v, ch2 5v, time base = 1 s/div ch2 ch1 v out scl t a = 25 c v dd = 5v figure 18. exiting power-down to midscale v dd (v) i dd ( a) 200 0 2.7 3.2 3.7 4.2 100 5 0 4.7 5.2 150 e40 c +25 c +105 c figure 13. supply current vs. supply voltage ch1 1v, time base = 5 s/div ch1 v out v dd = 5v t a = 25 c load = 2k and 200pf to gnd figure 16. half-scale settling (1/4 to 3/4 scale code charge) 1 s /div 2.50 2.49 2.48 2.47 v out (v) figure 19. major-code transition
rev. a ad5301/ad5311/ad5321 e9e 1ns/div v out (v) 2.440 2.455 2.445 2.450 figure 20. digital feedthrough general description the ad5301/ad5311/ad5321 are single resistor-string dacs fabricated on a cmos process with resolutions of 8, 10 and 12 bits, respectively. data is written via a 2-wire serial interface. they operate from single supplies of 2.5 v to 5.5 v and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 v/ s. the power-supply (v dd ) acts as the refer- ence to the dac. the devices have three programmable power- down modes, in which the dac may be turned off completely with a high impedance output, or the output may be pulled low by an on-chip resistor (see power-down section). digital-to-analog section the architecture of the dac channel consists of a resistor- string dac followed by an output buffer amplifier. the voltage at the v dd pin provides the reference voltage for the dac. figure 21 shows a block diagram of the dac architecture. since the input coding to the dac is straight binary, the ideal output voltage is given by v vd out dd n = 2 w here: n = dac resolution d = decimal equivalent of the binary code which is loaded to the dac register: 0e255 for ad5301 (8 bits) 0e1023 for ad5311 (10 bits) 0e4095 for ad5321 (12 bits) v dd v out gnd resistor string ref (+) ref (e) output buffer amplifier dac register figure 21. dac channel architecture resistor string the resistor string section is shown in figure 22. it is simply a string of resistors, each of value r. the digital code loaded to the dac register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic over all codes. r r r r rto output amplifier figure 22. resistor string output amplifier the output buffer amplifier is capable of generating output voltages to within 1 mv from either rail, which gives an output range of 0.001 v to v dd e 0.001 v. it is capable of driving a load of 2 k to gnd and v dd , in parallel with 500 pf to gnd. the source and sink capabilities of the output amplifier can be seen in figure 11. the slew r ate is 0.7 v/ s with a half-scale settling time to 0.5 lsb (at 8 bits) of 6 s with the output unloaded. power-on reset the ad5301/ad5311/ad5321 are provided with a power-on reset function, ensuring that they power up in a defined state. the dac register is filled with zeros and remains so until a valid write sequence is made to the device. this is particularly useful in applications where it is important to know the state of the dac output while the device is powering up.
rev. a ad5301/ad5311/ad5321 e10e x x pd1 pd0 d7 d6 d5 d4 d3 d2 d1 d0 x x x x db0 (lsb) db15 (msb) data bits figure 23a. ad5301 input shift register contents x x pd1 pd0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x db0 (lsb) db15 (msb) data bits figure 23b. ad5311 input shift register contents x x pd1 pd0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 db0 (lsb) db15 (msb) data bits figure 23c. ad5321 input shift register contents serial interface 2-wire serial bus the ad5301/ad5311/ad5321 are controlled via an i 2 c- compatible serial bus. the dacs are connected to this bus as slave devices (no clock is generated by the ad5301/ad5311/ ad5321 dacs). the ad5301/ad5311/ad5321 has a 7-bit slave address. in the case of the 6-lead device, the six msbs are 000110 and the lsb is de termined by the state of the a0 pin. in the case of the 8-lead device, the five msbs are 00011 and the two lsbs are determined by the state of the a0 and a1 pins. a1 and a0 allow the user to use up to four of these dacs on one bus. the 2-wire serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high. the following byte is the address byte that consists of the 7-bit slave address followed by an r/ w d w w d d wp p d d p d d p ddd d d dd d d d d pd d
rev. a ad5301/ad5311/ad5321 e11e scl sda scl sd ad 3d 2d 1d 0 xxxx xxpd1pd0 d7 d6 d5 d4 00011a1 * a0 r/ w ack by ad5301 stop cond by master least significant control byte ack by ad5301 start cond by master address byte most significant control byte ack by ad5301 * this bit must be 0 in the 6-lead sot-23 version. figure 24. ad5301 write sequence scl sda scl sda d5 d 4d3d2 d1d0 x x xxpd1pd0 d9 d8 d7 d6 000 11a1 * a0 r/ w ack by ad5311 stop cond by master least significant control byte ack by ad5311 start cond by master address byte most significant control byte ack by ad5311 * this bit must be 0 in the 6-lead sot-23 version. figure 25. ad5311 write sequence scl sda scl sda d7 d6 d 5d4 d3d2d1d0 xxpd1pd0 d11 d10 d9 d8 000 11a1 * a0 r/ w ack by ad5321 stop cond by master least significant control byte ack by ad5321 start cond by master address byte most significant control byte ack by ad5321 * this bit must be 0 in the 6-lead sot-23 version. figure 26. ad5321 write sequence write operation when writing to the ad5301/ad5311/ad5321 dacs, the user must begin with an address byte, after which the dac will acknowledge that it is prepared to receive data by pulling sda low. this address byte is followed by the 16-bit word in the f orm of two control bytes. the write operations for the three dacs are shown in the figures below.
rev. a ad5301/ad5311/ad5321 e12e read operation when reading data back from the ad5301/ad5311/ad5321 dacs, the user must begin with an address byte after which the dac will acknowledge that it is prepared to transmit data by pulling sda low. there are two different read operations. in the case of the a d5301, the readback is a single byte that consists scl sda 0 0 0 1 1 a1 * a0 r/ w * this bit must be 0 in the 6-lead sot-23 version. ack by ad5301 start cond by master address byte d7 d6 d5 d4 d3 d2 d1 d0 no ack by master stop cond by master data byte figure 27. ad5301 readback sequence scl sda scl sda d5 d 4d3d2 d1d0 x x xxpd1pd0 d9 d8 d7 d6 000 11a1 * a0 r/ w no ack by master stop cond by master least significant byte ack by ad5311 start cond by master address byte most significant byte ack by master * this bit must be 0 in the 6-lead sot-23 version. figure 28. ad5311 readback sequence scl sda scl sda d7 d6 d 5d4 d3d2d1d0 xxpd1pd0 d11 d10 d9 d8 000 11a1 * a0 r/ w no ack by master stop cond by master least significant byte ack by ad5321 start cond by master address byte most significant byte ack by master * this bit must be 0 in the 6-lead sot-23 version. figure 29. ad5321 readback sequence of the eight data bits in the dac register. however, in the case of the ad 5311 and ad5321, the readback consists of two bytes that contain both the data and the power-down mode bits. the read operations for the three dacs are shown in the figures below.
rev. a ad5301/ad5311/ad5321 e13e power-down modes the ad5301/ad5311/ad5321 have very low power consump- tion, dissipating typically 0.36 mw with a 3 v supply and 0.75 mw with a 5 v supply. power consumption can be further reduced when the dac is not in use by putting it into one of three power-down modes, which are selected by bits 13 and 12 (pd1 and pd0) of the control word. table i shows how the state of the bits corresponds to the mode of operation of the dac. table i. pd1/pd0 operating modes pd1 pd0 operating mode 00 normal operation 01 power-down (1 k load to gnd) 10 power-down (100 k load to gnd) 11 power-down (three-state output) the software power-down modes programmed by pd0 and pd1 may be overridden by the pd d pd wd d d p pwdw d w dpd d dd dd pp p dd d d d d w d p dd pdd d ddd dd d dwd d d a + (5 v /2 k ) = 2.65 ma the load regulation of the ref195 is typically 2 ppm/ma, which results in an error of 5.3 ppm (26.5 v) for the 2.65 ma current drawn from it. this corresponds to a 0.00136 lsb error. bipolar operation using the ad5301/ad5311/ad5321 the ad5301/ad5311/ad5321 has been designed for single- supply operation but a bipolar output range is also possible using t he circuit in figure 32. the circuit below will give an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or an op295 as the output amplifier. +5v 5v e5v ad820/ op295 2-wire serial interface +5v ad5301/ ad5311/ ad5321 10 f 0.1 f v dd v out r1 = 10k r2 = 10k figure 32. bipolar operation with the ad5301/ad5311/ ad5321
rev. a ad5301/ad5311/ad5321 e14e ad5301 a1 a0 sda scl v out ad5301 a1 a0 sda scl v out ad5301 a1 a0 sda scl v out ad5301 a1 a0 sda scl v out scl sda 5v v dd v dd v dd master r p r p figure 33. multiple ad5301 devices on one bus the output voltage for any input code can be calculated as v out = [( v dd ( d /2 n ) ( r 1 + r 2)/ r 1) e v dd ( r 2/ r 1)] where d is the decimal equivalent of the code loaded to the dac. n is the dac resolution. with v dd = 5 v, r1 = r2 = 10 k , v out = (10 d /2 n ) e 5 v multiple devices on one bus figure 33 shows four ad5301 devices on the same serial bus. each has a different slave address since the state of their a0 and a1 pins is different. this allows each dac to be written to or read from independently. the master device output bus line drivers are open-drain pull downs in a fully i 2 c-compatible interface. cmos driven scl and sda lines for single or multisupply systems where the minimum scl swing requirements allow it, a cmos scl driver may be used, the scl pull-up resistor can be removed, making the scl bus line fully cmos compatible. this will reduce power consump- tion in both the scl driver and receiver devices. the sda line remains open-drain, i 2 c compatible. further changes, in the sda line driver, may be made to make the system more cmos compatible and save more power. as the sda line is bidirectional, it cannot be made fully cmos compatible. a switched pull-up resistor can be combined with a cmos device with an open-circuit (three-state) input such that the cmos sda driver is enabled during write cycles and i 2 c mode is enabled during shared cycles, i.e., readback, acknowledge bit cycles, start and stop conditions. power supply decoupling in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the ad5301/ad5311/ad5321 should be decoupled to gnd with a 10 f in parallel with 0.1 f capacitor, located as close to the package as possible. the 10 f capacitor should be the tantalum bead type, while a ceramic 0.1 f capacitor will provide a sufficient low impedance path to ground at high frequencies. the power supply lines of the ad5301/ad5311/ad5321 should use as large a trace as possible to provide low impedance paths. a ground line routed between the sda and scl lines will help reduce crosstalk between them (not required on a multilayer board as there will be a ground plane layer but separating the lines will help).
rev. a ?5 ad5301/ad5311/ad5321 outline dimensions 6-lead small outline transistor package [sot-23] (rt-6) dimensions shown in millimeters 1 3 4 5 2 6 2.90 bsc pin 1 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 0.22 0.08 10 4 0 0.50 0.30 0.15 max 1.30 1.15 0.90 seating plane 1.45 max 0.60 0.45 0.30 compliant to jedec standards mo-178ab 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters 0.80 0.60 0.40 8 0 85 4 1 4.90 bsc pin 1 0.65 bsc 3.00 bsc seating plane 0.15 0.00 0.38 0.22 1.10 max 3.00 bsc coplanarity 0.10 0.23 0.08 compliant to jedec standards mo-187aa
rev. a ad5301/ad5311/ad5321 ?6 c00927??1/03(a) revision history location page 11/03?ata sheet changed from rev. 0 to rev. a. changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defined by philips.

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